用AD7606芯片采集信号，输出数据骤升，大概为0.94V，已排除输入源的问题，输出波形图如下，输入源是0.5v到3.5v的三角波
- //////////////////////////////////////////////////////////////////////////////////
- // //
- // //
- // Author: meisq //
- // msq@qq.com //
- // ALINX(shanghai) Technology Co.,Ltd //
- // heijin //
- // WEB: http://www.alinx.cn/ //
- // BBS: http://www.heijin.org/ //
- // //
- //////////////////////////////////////////////////////////////////////////////////
- // //
- // Copyright (c) 2017,ALINX(shanghai) Technology Co.,Ltd //
- // All rights reserved //
- // //
- // This source file may be used and distributed without restriction provided //
- // that this copyright statement is not removed from the file and that any //
- // derivative work contains the original copyright notice and the associated //
- // disclaimer. //
- // //
- //////////////////////////////////////////////////////////////////////////////////
- //================================================================================
- // Revision History:
- // Date By Revision Change Description
- //--------------------------------------------------------------------------------
- //2017/8/28 1.0 Original
- //*******************************************************************************/
- `timescale 1ns / 1ps
- module ad7606_if(
- input clk,
- input rst_n,
- input [15:0] ad_data, //ad7606 采样数据
- input ad_busy, //ad7606 busy忙标志位
- input first_data, //ad7606 first data第一个数据标志位
- input adc_flag, //ad7606 采集信号标志位
- input trans_end_flag,
- input fifo_flag ,
- output [2:0] ad_os, //ad7606 过采样倍率选择
- output reg ad_cs, //ad7606 AD cs
- output reg ad_rd, //ad7606 AD data read
- output reg ad_reset, //ad7606 AD reset
- output reg ad_convstab, //ad7606 AD convert start
- output reg ad_end_flag,
- output reg [15:0] ad_ch1,
- output reg [15:0] ad_ch2,
- output reg [15:0] ad_ch3,
- output reg [15:0] ad_ch4,
- output reg [15:0] ad_ch5,
- output reg [15:0] ad_ch6,
- output reg [15:0] ad_ch7,
- output reg [15:0] ad_ch8
-
- );
- reg [15:0] rst_cnt;
- reg [5:0] i;
- reg [3:0] state = 0;
- reg adc_flag0;
- reg adc_flag1;
- reg fifo_flag0;
- reg fifo_flag1;
- reg cnt_flag;
- reg [19:0] cnt_adc_end;
- parameter IDLE=4'd0;
- parameter AD_CONV=4'd1;
- parameter Wait_1=4'd2;
- parameter Wait_busy=4'd3;
- parameter READ_CH1=4'd4;
- parameter READ_CH2=4'd5;
- parameter READ_CH3=4'd6;
- parameter READ_CH4=4'd7;
- parameter READ_CH5=4'd8;
- parameter READ_CH6=4'd9;
- parameter READ_CH7=4'd10;
- parameter READ_CH8=4'd11;
- parameter READ_DONE=4'd12;
- assign ad_os=3'b001;
- wire adc_start_flag ;
- wire adc_stop_flag;
- wire adc_fifo_flag;
- //
- //assign adc_start_flag=0;
- assign adc_start_flag = adc_flag0 & (~adc_flag1); //上升沿判断
- assign adc_stop_flag = (~adc_flag0) & adc_flag1;
- assign adc_fifo_flag = fifo_flag0 & (~fifo_flag1);
- //当脉冲信号end_flag到达时，将电平延迟2个数据，用以判断沿
- always @(posedge clk or negedge rst_n) begin
- if(!rst_n) begin
- adc_flag0 <= 0;
- adc_flag1 <= 0;
- end
- else begin //将数据延迟2位，用以判断沿
- adc_flag0 <= adc_flag;
- adc_flag1 <= adc_flag0;
- end
- end
- always @(posedge clk or negedge rst_n) begin
- if(!rst_n) begin
- fifo_flag0 <= 0;
- fifo_flag1 <= 0;
- end
- else begin //将数据延迟2位，用以判断沿
- fifo_flag0 <= fifo_flag;
- fifo_flag1 <= fifo_flag0;
- end
- end
- ////adc采集次数计数
- //always @(posedge clk or negedge rst_n) begin
- // if(!rst_n) begin
- // cnt_adc_end <= 0;
- // end
- // else if(cnt_adc_end == 18'd180000) begin
- // cnt_adc_end <= 0;
- // cnt_flag <= 0;
- // end
- // else if(ad_end_flag == 1 )
- // cnt_adc_end <= cnt_adc_end + 1;
- //end
- always@(posedge clk or negedge rst_n)
- begin
- if(rst_n == 1'b0)
- begin
- rst_cnt <= 16'd0;
- ad_reset <= 1'b1;
- end
- else if(rst_cnt == 16'hffff)
- begin
- ad_reset <= 1'b1;
- rst_cnt <= rst_cnt + 16'd1;
- end
- else begin
- ad_reset <= 1'b0;
- end
- end
- always@(posedge clk)
- begin
- if(ad_reset==1'b1)
- begin
- state <= IDLE;
- ad_ch1 <= 0;
- ad_ch2 <= 0;
- ad_ch3 <= 0;
- ad_ch4 <= 0;
- ad_ch5 <= 0;
- ad_ch6 <= 0;
- ad_ch7 <= 0;
- ad_ch8 <= 0;
- ad_cs <= 1'b1;
- ad_rd <= 1'b1;
- ad_convstab <= 1'b1;
- i <= 6'd0;
- ad_end_flag <= 0;
- end
- else if (adc_start_flag)
- cnt_flag <= 1'b1;
- else if (adc_stop_flag) //adc_stop_flag ||
- cnt_flag <= 1'b0;
- // else if (cnt_adc_end == 20'd540000) begin
- // cnt_adc_end <= 0;
- // cnt_flag <= 1'b0;
- //
- // end
- else if(cnt_flag)begin
- case(state)
- IDLE:
- begin
-
- ad_cs<=1'b1;
- ad_rd<=1'b1;
- ad_convstab<=1'b1;
- if(i==20) begin
- i <= 6'd0;
- state<=AD_CONV;
- end
- else
- i <= i + 6'd1;
- ad_end_flag <= 1'b0;
- end
- AD_CONV:
- begin
- if(i==2)
- begin //wait 2 clock
- i <= 6'd0;
- state<=Wait_1;
- ad_convstab<=1'b1;
- end
- else
- begin
- i <= i + 6'd1;
- ad_convstab<=1'b0; //启动AD转换
- end
- ad_end_flag <= 1'b0;
- end
- Wait_1:
- begin
- if(i==5)
- begin //wait 5 clock 等待busy信号为高
- i <= 6'd0;
- state<=Wait_busy;
- end
- else
- i <= i + 6'd1;
- ad_end_flag <= 1'b0;
- end
- Wait_busy:
- begin
- if(ad_busy==1'b0)
- begin //wait busy low 等待busy信号为低
- i <= 6'd0;
- state<=READ_CH1;
- end
- ad_end_flag <= 1'b0;
- end
- READ_CH1:
- begin
- ad_cs<=1'b0; //cs valid 信号有效
- if(i==3)
- begin
- ad_rd<=1'b1;
- i <= 6'd0;
- ad_ch1<=ad_data; //read CH1
- state<=READ_CH2;
- end
- else
- begin
- ad_rd<=1'b0;
- i <= i + 6'd1;
- end
- ad_end_flag <= 1'b0;
- end
- READ_CH2:
- begin
- if(i==3)
- begin
- ad_rd<=1'b1;
- i <= 6'd0;
- ad_ch2<=ad_data; //read CH2
- // state<=READ_DONE;
- state<=READ_CH3;
- end
- else
- begin
- ad_rd<=1'b0;
- i <= i + 6'd1;
- end
- ad_end_flag <= 1'b0;
- end
- READ_CH3:
- begin
- if(i==3)
- begin
- ad_rd<=1'b1;
- i <= 6'd0;
- ad_ch3<=ad_data; //read CH3
- state<=READ_CH4;
- end
- else
- begin
- ad_rd<=1'b0;
- i <= i + 6'd1;
- end
- ad_end_flag <= 1'b0;
- end
- READ_CH4:
- begin
- if(i==3)
- begin
- ad_rd<=1'b1;
- i <= 6'd0;
- ad_ch4<=ad_data; //read CH4
- state<=READ_CH5;
- end
- else
- begin
- ad_rd<=1'b0;
- i <= i + 6'd1;
- end
- ad_end_flag <= 1'b0;
- end
- READ_CH5:
- begin
- if(i==3)
- begin
- ad_rd<=1'b1;
- i <= 6'd0;
- ad_ch5<=ad_data; //read CH5
- state<=READ_CH6;
- end
- else
- begin
- ad_rd<=1'b0;
- i <= i + 6'd1;
- end
- ad_end_flag <= 1'b0;
- end
- READ_CH6:
- begin
- if(i==3)
- begin
- ad_rd<=1'b1;
- i <= 6'd0;
- ad_ch6<=ad_data; //read CH6
- state<=READ_CH7;
- end
- else
- begin
- ad_rd<=1'b0;
- i <= i + 6'd1;
- end
- ad_end_flag <= 1'b0;
- end
- READ_CH7:
- begin
- if(i==3)
- begin
- ad_rd<=1'b1;
- i <= 6'd0;
- ad_ch7<=ad_data; //read CH7
- state<=READ_CH8;
- end
- else
- begin
- ad_rd<=1'b0;
- i <= i + 6'd1;
- end
- ad_end_flag <= 1'b0;
- end
- READ_CH8:
- begin
- if(i==3)
- begin
- ad_rd<=1'b1;
- i <= 6'd0;
- ad_ch8<=ad_data; //read CH8
- state<=READ_DONE;
- end
- else
- begin
- ad_rd<=1'b0;
- i <= i + 6'd1;
- end
- ad_end_flag <= 1'b0;
- end
- READ_DONE:
- begin
- ad_rd<=1'b1;
- ad_cs<=1'b1;
- state<=IDLE;
- cnt_adc_end <= cnt_adc_end + 1;
- if(trans_end_flag)
- ad_end_flag <= 1'b1;
- end
- default:
- state<=IDLE;
- endcase
- end
- end
- endmodule
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