为什么ISE无法将时钟路由到IODELAY2块？

我正在连接一个DDR比特率为720 Mhz的ADC。
输入时钟是@ 360 Mhz的差分，它的边缘以数据窗口为中心。
我在输入时钟上使用IBUFGDS_DIFF_OUT缓冲区。
我尝试使用IOSERDES的典型设置，其中时钟IODELAY2设置为固定延迟0.对于数据的IODELAY2配置为“DIFF_PHASE_DETECTOR”和“WRAPAROUND”，我发现分接计数器在接近零处运行。
偏斜的任何偏移都会导致计数器换行，并且serdes会失去位同步。
设置为“STAY_AT_LIMIT”似乎不适用于“负”时钟偏差。
因此，为了避免在接近极限的情况下运行计数器，我接下来尝试设置时钟的主设备和从设备IODELAY2，以便可以将其校准为HALF_MAX。
以下是主IODELAY2的配置：
DATA_RATE =>“DDR”，
IDELAY_MODE =>“正常”，
SERDES_MODE =>“MASTER”，
IDELAY_TYPE =>“VARIABLE_FROM_HALF_MAX”，
COUNTER_WRAPAROUND =>“STAY_AT_LIMIT”
端口映射（IDATAIN => iob_data_in_p，
。
。
IOCLK0 => iob_data_in_p，
IOCLK1 => iob_data_in_n，
。
。
CAL => iCal_master， - 校准启用信号
从属IODELAY的配置类似，除了：
SERDES_MODE =>“SLAVE”
IDATAIN => iob_data_in_n，
IOCLK0 => iob_data_in_n，
IOCLK1 => iob_data_in_p，
这在Modelsim中完美运行。
在“iCal_master”被置位后，时钟延迟半个周期。
问题是ISE（13.1和14.2都尝试过）无法路由时钟iob_data_in_p和iob_data_in_n。
除了这些IODELAY2之外，这些时钟没有其他负载。
所以，我的问题是：
1.为什么ISE无法将时钟路由到IODELAY2块？
2.当输入时钟已经居中以避免计数器换行问题时，正确的设置是什么？
在这个时钟周期，时钟的固定延迟可能不会对所有P，V和T起作用，因为几乎有3到1的变化。
我很感激任何建议。



以下为原文

I am interfacing an ADC with a DDR bit rate of 720 Mhz. The input clock is differential in @360 Mhz and it's edges are centered on the data window. I am using an IBUFGDS_DIFF_OUT buffer on the input clock. I have tried using the typical setup of the IOSERDES where the clock IODELAY2 is set to a fixed delay of 0. With the data's IODELAY2 configured for "DIFF_PHASE_DETECTOR" and "WRAPAROUND" I found the tap counter runs at near zero. Any shift in skew causes the counter to wrap and the serdes looses bit sync.
Setting to "STAY_AT_LIMIT" doesn't appear to work with "negative" clock skew.

So, to get away from running the counter at near it's limit, I next tried setting up the clock's master and slave IODELAY2 such that it can be calibrated to HALF_MAX. Here is the the configuration for the master IODELAY2:

    DATA_RATE              => "DDR",
IDELAY_MODE           => "NORMAL",
SERDES_MODE           => "MASTER",
    IDELAY_TYPE           => "VARIABLE_FROM_HALF_MAX",
COUNTER_WRAPAROUND     => "STAY_AT_LIMIT"
port map (
    IDATAIN          => iob_data_in_p,
.
.
    IOCLK0           => iob_data_in_p,
    IOCLK1           => iob_data_in_n,
.
.
    CAL              => iCal_master,         -- Calibrate enable signal


The slave IODELAY is configured similarly except:

SERDES_MODE           => "SLAVE"
IDATAIN         => iob_data_in_n,
IOCLK0            => iob_data_in_n,
IOCLK1           => iob_data_in_p,

This works perfectly in Modelsim. After "iCal_master" is asserted the clock is delayed by one half period.


The problem is ISE (tried both 13.1 and 14.2)  is unable to route the clocks iob_data_in_p and iob_data_in_n. Other than these IODELAY2's, these clocks have no other loads.

So, my questions are:

1. Why is ISE unable to route the clocks into the IODELAY2 blocks ?

2. What is the correct set up when the input clock is already centered to avoid the counter wrap issue ?  At this clock period a fixed delay of the clock probably won't work over all P,V and T since there is nearly a 3 to 1 variation.

I'd appreciate any suggestions.