vhdl中的两个计数器实现有什么区别

正如您在原始消息中所述，您的两段代码的实现是相同的。
在进程内部分配但在任何if语句之外或分配为连续语句之间没有实现差异。
模拟可能存在差异，因为“过程”分配仅在过程处于活动状态时发生。
这可能导致模拟/实现不匹配。
在这种情况下，您只需要连续分配，我认为最好将其分配到任何流程之外。
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德
在原帖中查看解决方案



以下为原文

As you noted in your original message, the implementation of your two pieces of code is the same. There is no implementation difference between assigning inside a process but outside any if statement or assigning as a continuous statement.
 
There may be a difference in simulation, as the "process" assignment will only occur when the process is active. This may then lead to simulation/implementation mismatch.
 
In this context, where you just want a continuous assignment, I think it is better to assign it outside of any process.
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"That which we must learn to do, we learn by doing." - AristotleView solution in original post

您好，第一种方法是正确和适当的。
您应该始终在处理后分配信号的值。对于第二种方法，您应该看到工具的警告
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如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-
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以下为原文

Hello,

first method is correct and appropriate. You should always assign the value of signal after the process.

For 2nd method you should see the warning from the tool-Pratham

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两件事情：
1.不要使用std_logic_unsigned库。
它不是标准的（尽管它的名字）并且在每个方面都被numeric_std取代（你有但实际上并没有使用）。
2.使用整数计数器而不是std_logic_vectors。
std_logic_vectors不要暗示值信息 - 它们只是一串位，因此使用了垃圾std_logic_unsigned库。
更好的（至少在视觉上）计数器实现可以是：
图书馆;
使用ieee.std_logic_1164.all;
使用ieee.numeric_std.all;
实体柜台是 
港口 （ 
clk：在STD_LOGIC中; 
reset：在STD_LOGIC中; 
count：OUT std_logic_vector（3 downto 0） 
）;
终点;
建筑的行为是
- 定义计数器限制。
矢量长度为2的幂
- 例如
对于4位计数器限制是2 ** 4 = 16。
- 使用'LENGTH属性允许计数器
- 只需更改输入的宽度即可轻松扩展。
- 模数计数器将在其自身环绕时
- 达到终端计数 
常数COUNT_MAX：整数：= 2 ** count'LENGTH;
- 定义实际的计数器信号 
signal i_count：整数范围0到COUNT_MAX-1：= 0;
开始
- 每个时钟周期递增的过程
- 不使用重置（本例不需要重置）
- 但如果需要可以轻松添加
P_COUNTER：进程（时钟）是
开始 
如果rising_edge（时钟）那么 
我算 
万一;
结束过程P_COUNTER;
- 连续分配矢量输出
- 如有必要，可在流程中注册
计数
最终行为;
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

Two things:
 
1. DON'T use the std_logic_unsigned library. It's not standard (despite it's name) and is superseded in every respect by numeric_std (which you have but dont actually use).
2. Use integer counters and not std_logic_vectors. std_logic_vectors DO NOT imply value information - they are just a string of bits, hence the use of the rubbish std_logic_unsigned library.
 
A far better (at least, visually) counter implementation could be:
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity counter is
  port (
    clk : in STD_LOGIC;
    reset: in STD_LOGIC;
    count : OUT std_logic_vector ( 3 downto 0)
  );
end counter;
 
architecture Behavioral of counter is
 
-- Define the counter limit. A power of 2 of the vector length
-- e.g. for a 4 bit counter limit is 2**4 = 16.
-- Using the 'LENGTH attribute allows the counter to
-- expand easily simply by changing the width of the input.
-- A modulo counter will wrap around on its own when
-- the terminal count is reached
  constant COUNT_MAX : integer := 2**count'LENGTH;
 
-- Define the actual counter signal
  signal i_count : integer range 0 to COUNT_MAX-1 := 0;
 
begin
 
-- Process to increment per clock cycle
-- No reset is used (not really needed for this example)
-- but can easily be added if required
P_COUNTER : process(clock) is
begin
  if rising_edge(clock) then
    i_count <= (i_count + 1) mod COUNT_MAX;
  end if;
end process P_COUNTER;
 
-- Continuous assignment to the vector output
-- this could be registered in a process if necessary
count <= std_logic_vector(to_unsigned(i_count, count'LENGTH));
 
end behavioural;
----------
"That which we must learn to do, we learn by doing." - Aristotle

Thnaks详细回复。
在我看过的所有文本中，计数器输出分配都是在进程外完成的。
我打算问的是，如果我在流程中分配它有什么区别。
是否有任何应用程序可能需要内部流程分配？



以下为原文

Thnaks for the detailed reply. In all the text i have seen the counter output assignment is done outside the process. What i intended to ask is that what is the difference if i assign it inside the process. Is there any application where i may need the inside process assignment?

正如您在原始消息中所述，您的两段代码的实现是相同的。
在进程内部分配但在任何if语句之外或分配为连续语句之间没有实现差异。
模拟可能存在差异，因为“过程”分配仅在过程处于活动状态时发生。
这可能导致模拟/实现不匹配。
在这种情况下，您只需要连续分配，我认为最好将其分配到任何流程之外。
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

As you noted in your original message, the implementation of your two pieces of code is the same. There is no implementation difference between assigning inside a process but outside any if statement or assigning as a continuous statement.
 
There may be a difference in simulation, as the "process" assignment will only occur when the process is active. This may then lead to simulation/implementation mismatch.
 
In this context, where you just want a continuous assignment, I think it is better to assign it outside of any process.
----------
"That which we must learn to do, we learn by doing." - Aristotle

pratibhas写道：
Thnaks详细回复。
在我看过的所有文本中，计数器输出分配都是在进程外完成的。
我打算问的是，如果我在流程中分配它有什么区别。
是否有任何应用程序可能需要内部流程分配？
您有一个名为i_count的实体内部信号，该信号由进程更新。
您希望计数器值是实体的输出。
您应该在进程外部具有连续分配计数，因为如果它在进程内部，则它将仅更新进程敏感性列表中的任何更改（在本例中为时钟）。
这不是你想要的结果。
您希望i_count中的更改立即反映在count上，因此您必须在该过程之外进行分配。
----------------------------是的，我这样做是为了谋生。



以下为原文

pratibhas wrote:
Thnaks for the detailed reply. In all the text i have seen the counter output assignment is done outside the process. What i intended to ask is that what is the difference if i assign it inside the process. Is there any application where i may need the inside process assignment?

You have a signal internal to the entity called i_count, which is updated by the process. You want the counter value to be the entity's output. You should have the continuous assignment count <= i_count; outside the process because if it is inside the process, it will only update on changes in whatever is on the process sensitivity list (the clock, in this case). That's not the result you want. You want to have the changes in i_count reflected immediately on count, hence you have to do the assignment outside the process.
----------------------------Yes, I do this for a living.

你能告诉我如何添加重置到这个柜台。
我试过但总是Vivado stps错误。
谢谢



以下为原文

Can you tell please how add reset to this counter. i tried but always Vivado stps in error.
Thank you

你能分享你的代码和Vivado给你的错误吗？
向计数器添加重置与向任何其他VHDL进程添加重置完全相同。
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

Could you share your code and the error that Vivado gives you?
 
Adding a reset to a counter is pretty much exactly the same as adding a reset to any other VHDL process.
----------
"That which we must learn to do, we learn by doing." - Aristotle