怎么实现两个32位计数器计数速率高达3GHz

嗨，
虽然我在90年代曾使用过CPLD，但我还不熟悉FPGA。
我有一个项目的想法，如果可能的话我正在考虑FPGA解决方案。
但在让自己成为开发板并潜入之前，我想我会先在这里得到一些建议。
基本上我想实现两个32位计数器，但我希望这些计数器的计数速率高达3GHz。
看起来低端FPGA（即Spartan 6）的最大频率为200  -  300 MHz。
因此，我计划使用离散ECL逻辑在片外实现4个LSB，并在FPGA中实现每个计数器的剩余28位。
然后将外部4位引入FPGA，并且两个32位计数器将由加法器求和，然后主机处理器可以读取结果。
虽然外部4位仍然会在FPGA的频率过高时切换，但在对计数器求和之前，时钟将停止。
如果需要，我可以对这些输入进行门控，并且只有在时钟停止后才启用它们。
将会有一些额外的逻辑，可能还有第三个计数器，但我意识到Spartan 6可能有点过分，但我主要对更高的时钟速度感兴趣。
任何意见将不胜感激。
谢谢。
问候，
抢



以下为原文

Hi,

Although I have used CPLDs back in the 90s I am new to FPGAs. I have an idea for a project for which I am considering an FPGA solution if possible. But before getting myself a development board and diving in I thought I would get some advise here first.

Basically I want to implement two 32 bit counters but I want these counters counting at a rate up to 3GHz. It appears that the max frequency for a low end FPGA (ie. Spartan 6) is 200 - 300 MHz. Therefore I was planning to implement the 4 LSBs off chip using discrete ECL logic and implement the remaining 28 bits of each counter in the FPGA. The external 4 bits would then be brought into the FPGA and both 32 bit counters would be summed by an adder and the result could then be read by the host processor. Although the external 4 bits would still be toggling at frequencies too high for the FPGA, the clocks will be stopped before summing the counters. If necessary I could gate these inputs and only enable them once the clocks have stopped. There will be some additional logic and possibly a third counter but I realise the Spartan 6 is probably a bit of overkill but I'm mainly interested in the higher clock speeds.

Any comments would be appreciated. Thanks.

Regards,
Rob