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嗨,
我一直在尝试使用外部时钟驱动一些AXI外设,尽管该设计已经过测试,使用相同频率的内部时钟(Zynq PLL生成),但在使用外部时钟时无法运行。 分机 时钟通过时钟使能引脚提供,路由到MMCM,通过Zynq复位输出复位,MMCM的锁定输出连接到处理器系统复位外设的相应输入,确保时钟稳定,然后允许外设/互连操作 。 Zynq处理器的AXI时钟接口也由同一时钟驱动。 我错过了什么? :) 谢谢, 本 以上来自于谷歌翻译 以下为原文 Hi, I have been attempting to drive some AXI peripherals using an external clock, although the design has been tested working with an internal clock (Zynq PLL generated) of the same frequency, it fails to operate when the external clock is used. The ext. clock is fed via a clock enable pin, routed to a MMCM which resets by the Zynq reset output, the locked output from MMCM is connected to corresponding input of the Processor Sys Reset peripheral ensuring the clock is stabilised before peripherals/interconnects are permitted to operate. The AXI clocking interface of the Zynq processor is also driven by the same clock. What have I missed? :) Thanks, Ben |
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刚刚在不使用复位输入(MMCM)的情况下实现了设计并确认了解决方案的有效性。
谢谢, 本 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Just implemented the design without using the Reset input (MMCM) and confirmed the solution works. Thanks, Ben View solution in original post |
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嗨,
看起来“由Zynq复位输出复位的MMCM”可能不起作用,因为两者的极性不同。 时钟转发器IP复位为低电平有效,Zynq PS复位为高电平有效。 它们之间的连接将在IPI块验证上引发错误。 尝试使用截图中显示的内容。 问候 P.V -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- -------------------------------------------------- -----------------------不要忘记回答,kudo,并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Hi, It looks like "a MMCM which resets by the Zynq reset output" may not work as the polarity of both are different. Clock conterter IP reset is active low and Zynq PS reset is active high. The connections between them will throw error on IPI block validation. Try to use as shown in screenshot. Regards P.V --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- ------------------------------------------------------------------------- Don’t forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
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嗨P.V.
根据我的配置,MMCM的复位输入实际配置为低电平有效,与PS的复位信号输出匹配。 其余的安排与您的相同。 考虑到具有处理器复位外设的dcm锁定接口的实现,可能不需要复位输入。 您能否确认所示设计是否有效或是否仅用于说明目的? 谢谢, 本 以上来自于谷歌翻译 以下为原文 Hi P.V. With my configuration, the Reset input of MMCM is actually configured as active low, matches with the output of the reset signal from the PS. The rest of the arrangement is identical to yours. Perhaps the reset input is not necessary, given the implementation of the dcm locked interface with the Processor Reset Peripheral. Could you confirm if the illustrated design is functional or is it just aimed for illustration purpose? Thanks, Ben |
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刚刚在不使用复位输入(MMCM)的情况下实现了设计并确认了解决方案的有效性。
谢谢, 本 以上来自于谷歌翻译 以下为原文 Just implemented the design without using the Reset input (MMCM) and confirmed the solution works. Thanks, Ben |
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