不使用处理器的I2C控制器

你想用串行EEPROM做什么？
目前还不清楚“控制”串行EEPROM是什么意思，因为通常你只是在读取或写入数据。
从本质上讲，I2C协议本身非常简单。
因此，如果没有处理器，您如何着手设计I2C接口取决于您想要实现的目标。
opencores上有代码可用于此（我自己没有尝试过，所以我不会评价它的实用性）。
我编写了代码，用于处理具有7位I2C地址和不超过1个地址字节的简单I2C从器件（如2Kbit EEPROM，以及使用I2C设置内部寄存器的典型I / O扩展器和视频器件）。
-  Gabor



以下为原文

What exactly do you want to do with the serial EEPROM's?  It's not clear what you mean by "control" serial EEPROM's, since normally you'd just eithe read or write data to them.
 
In essence, the I2C protocol itself is fairly simple.  So without a processor, how you set about designing an interface to I2C depends on what exactly you want to accomplish.  There is code available on opencores for this (haven't tried it myself so I won't rate its usefulness).  I have written code for dealing with simple I2C slaves with 7-bit I2C address and no more than 1 address byte (like a 2Kbit EEPROM, and typical of I/O expanders and video devices that use I2C for setup of internal registers).
-- Gabor

fatihdag写道：
嗨，
我需要一个I2C内核来控制串行eeprom。
在Web上的大多数I2C示例中，使用了微处理器。
但我想只使用FPGA。
我怎样才能做到这一点？
有没有人有I2C控制器，不需要处理器或微控制器？
谢谢。
我将从恩智浦网站上提供的I2C规范开始。
由于您的主人只处理已知的奴隶，因此大大简化了问题。
您不必担心多主仲裁，您可能不必处理等待状态。
基本上，它归结为状态机和几个移位寄存器。
----------------------------是的，我这样做是为了谋生。



以下为原文

fatihdag wrote:
Hi,
I need a I2C Core to control serial eeprom's. In most of the I2C examples on the web, microprocessors are used. But I want use only FPGA. How can i do that? and Does anyone have I2C controller which doesn't require processor or microcontroller?
Thanks.

I would start with the I2C spec, available from the NXP web site.
Since your master is dealing only with known slaves, it greatly simplifies the problem. You don't need to worry about multi-master arbitration, and you probably don't have to deal with wait states. 
Basically, it boils down to a state machine and a couple of shift registers.
----------------------------Yes, I do this for a living.

首先感谢您的关注。
首先，我只想将一个字节数据写入eeprom，直到获得经验。
来自opencores的大多数示例包括mp或wishbone控制器信号。
这对我来说更复杂。
我目前无法编写自己的i2c代码。
所以我尝试了现有代码的工作。
我从事过i2c理论。
我也研究了eeprom的数据表。
我只想用i2c协议发送总共35位（起始设备类型标识符-ack-byte adress-ack-data byte-ack-stop）。
谢谢。



以下为原文

First of all thank you for your interest.
Firstly I just want to write one byte data to an eeprom until getting the experience. Most of the examples from opencores includes mp or wishbone controller signal. It comes more complicated to me. I couldn't write my own i2c codes at the moment. So I try the work on existed codes. I'have worked i2c theory. Also I studied on the datasheet of the eeprom. I just want to send totally 35 bits (start-device type identifier-ack-byte adress-ack-data byte-ack-stop) with i2c protocol. 
Thanks.

看看这个目录：http：//www.fpga4fun.com/I2C.htmlit有一个简单的i2c代码，您可以使用它来实现i2c控制器并将其连接到chipscope vio以手动执行读/写操作。
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

look at this directory: http://www.fpga4fun.com/I2C.html

it has a simple i2c code which you can use to implement  an i2c controller and connect it to chipscope vio to do reads/writes manually.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

亲爱的大家，
我对fpgas和学习porpuses相当新，我正在用VHDL开发一个I2C模块。
我遇到了i2c时钟的问题，因为它与我创建的信号不同步，我不知道为什么。
我将把代码放在这里以及ISim wave的屏幕截图，希望有人可以暗示我做错了什么。
我知道模块还没有准备好..
图书馆IEEE;
使用IEEE.STD_LOGIC_1164.ALL;
- 如果使用，取消注释以下库声明
- 带有符号或无符号值的算术函数
- 使用IEEE.NUMERIC_STD.ALL;
- 如果实例化，则取消注释以下库声明
- 此代码中的任何Xilinx原语。
- 图书馆UNISIM;
- 使用UNISIM.VComponents.all;
实体i2c是 
端口（clk：在STD_LOGIC; 
reset：在STD_LOGIC中; 
i2c_sda：out STD_LOGIC; 
i2c_scl：out STD_LOGIC）;
结束i2c;
建筑行为的i2c是
常量IDLE：std_logic_vector：=“000”;
常数START：std_logic_vector：=“001”;
常数地址：std_logic_vector：=“010”;
常数RW：std_logic_vector：=“011”;
常量ACK：std_logic_vector：=“100”;
恒定的数据和结肠;
std_logic_vector：=“101”;
常量ACK2：std_logic_vector：=“110”;
常量STOP：std_logic_vector：=“111”;
signal addr：std_logic_vector（6 downto 0）：=（其他=>'0'）;
signal dat：std_logic_vector（6 downto 0）：=（其他=>'0'）;
signal i2c_scl_signal：std_logic;
信号状态：std_logic_vector（2 downto 0）;
开始
I2C：进程（clk）
变量计数器：整数范围0到7;
开始
如果falling_edge（clk）那么
如果reset ='1'那么
i2c_scl_signal i2c_scl_signal
万一;
万一;
如果rising_edge（clk）那么
如果reset ='1'那么
州
I2C_SDA
I2C_SDA
I2C_SDA
I2C_SDA
州
I2C_SDA
州
i2c_sda状态
更具体地说，当我进入地址状态时，在时钟的下降沿，i2c_scl和i2c_scl_signal都应该从1变为0（黄色标记所在的位置）但是信号会这样做而i2c_scl不会。
这最后一波等待一段时间从1变为0 ..为什么？
我将一些粗体代码放在一起，以便您更轻松地跟踪问题。
预先感谢您的帮助！



以下为原文

Dear all,
 
I fairly new to fpgas and for learning porpuses I am developing a I2C Module in VHDL.
 
I am having trouble with the i2c clock because it is not in phase with a signal that I created and I don't know why.
 
I will put the code in here as well as a screenshot of the ISim wave in hope that someone could give a hint on what I am doing wrong. I know that the module is not ready..
 
library IEEE;use IEEE.STD_LOGIC_1164.ALL;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity i2c is    Port ( clk : in  STD_LOGIC;           reset : in  STD_LOGIC;           i2c_sda : out  STD_LOGIC;           i2c_scl : out  STD_LOGIC);end i2c;architecture Behavioral of i2c isconstant IDLE : std_logic_vector :="000";constant START : std_logic_vector :="001";constant ADDRESS :  std_logic_vector :="010";constant RW :  std_logic_vector :="011";constant ACK :  std_logic_vector :="100";constant DATA :  std_logic_vector :="101";constant ACK2 :  std_logic_vector :="110";constant STOP :  std_logic_vector :="111";signal addr: std_logic_vector (6 downto 0) := (others => '0');signal dat: std_logic_vector (6 downto 0) := (others => '0');signal i2c_scl_signal: std_logic;signal state: std_logic_vector (2 downto 0);beginI2C: Process(clk)variable Counter : integer range 0 to 7;beginif falling_edge(clk) thenif reset = '1' theni2c_scl_signal <= '1';elsif state = IDLE or state = START or state = STOP theni2c_scl_signal <= '1';elsei2c_scl_signal <= not i2c_scl_signal;i2c_scl <= i2c_scl_signal;end if;end if;if rising_edge(clk) thenif reset = '1' thenstate <= IDLE;i2c_sda <= '1';i2c_scl <= '1';addr <= "0110000";dat <= "0011100";Counter := 0;end if;case state iswhen IDLE =>i2c_sda <= '1';state <= START;when START =>i2c_sda <= '0';state <= ADDRESS;Counter := 6;when ADDRESS =>i2c_sda <= addr(Counter);if Counter = 0 then state <= RW;else Counter := Counter -1;end if;when RW =>i2c_sda <= '1';state <= ACK;when ACK =>state <= DATA;Counter := 7;when DATA =>i2c_sda <= dat(Counter);if Counter = 0 then state <= ACK2;else Counter := Counter - 1;end if;when ACK2 =>state <= STOP;when STOP =>i2c_sda <= '1';state <= IDLE;when others => state <= IDLE;end case;end if;end Process I2C;end Behavioral; 
 
To be more specific, when I enter in the Address state, at the falling edge of the clock, both i2c_scl and i2c_scl_signal should go from 1 to 0 (where the yellow mark is) but the signal does that and the i2c_scl doesn't. This last wave waits one period to go from 1 to 0..why? I put some of the code in bold to be easier for you to track the problem.
 
Thank you in advance for your help!

> i2c_scl和i2c_scl_signal都应该从1到0（
你正在使用一个非阻塞的分配，所以这将i2c_scl永远是i2c_scl_signal后面的一个下降沿时钟周期（如果你不想要这个，那你为什么用这种方式写它）。
除了在rising_edge中遇到重置的争用时。
您需要在设计中使用单个时钟边沿，因为您编写的代码不可合成。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> both i2c_scl and i2c_scl_signal should go from 1 to 0 (
 
You are using a non-blocking assigments so this will i2c_scl will always be one falling edge clock cycle behind i2c_scl_signal (if you didn't want this then why did you write it this way).  Except for when it runs into a contention with a reset in the rising_edge.
 
You need to use a single clock edge in your design as the code that you wrote is not synthesizable.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

>您正在使用非阻塞分配，因此i2c_scl将始终是i2c_scl_signal后面的一个下降沿时钟周期（如果您不想要这个，那么为什么用这种方式编写它）。
除了在rising_edge中遇到重置的争用时。
好吧，我没有故意这样做。
阅读完您的帖子后，我会阅读有关阻止和非阻止分配的内容。
据我所知，如果我错了，请纠正我，使用“分配信号”
所以，解决这个问题我相信可以将i2c_scl_signal设置为变量而不是信号，但ISim不允许绘制变量，对调试很有用。
有任何替代解决方案，或者我真的必须在这种情况下使用变量？
>您需要在设计中使用单个时钟边缘，因为您编写的代码不可合成。
不知道那个。
你的意思是我的代码中没有或出于任何特定原因？
例如，如果我使用rising_edge（clk）和falling_edge（clk2）......不同的时钟......这有效吗？



以下为原文

>You are using a non-blocking assigments so this will i2c_scl will always be one falling edge clock cycle behind i2c_scl_signal (if you didn't want this then why did you write it this way).  Except for when it runs into a contention with a reset in the rising_edge.
 
Well I didn't do it on purpose. After reading your post I read about blocking and non-blocking assigments. As far as I understood, and please correct me if I am wrong, signals are assigned using "<=", and they are always non-blocking and variables, for instance, are assigned using ":=" this assignment is blocking. As I am trying to use the same signal twice on the same clock edge, one of the assignments will be done one clock later.
 
So, so solve this I believe that could set the i2c_scl_signal as variable instead of signal however ISim doesn't allow to plot variables, useful for debugging. There is any alternative solution or I really have to use variables in this case?
 
>You need to use a single clock edge in your design as the code that you wrote is not synthesizable.
Didn't know that. You mean never or for any specific reason in my code? What for instance if I were using rising_edge(clk) and falling_edge(clk2)...different clocks..is this valid?

nnunes写道：
不知道那个。
你的意思是我的代码中没有或出于任何特定原因？
例如，如果我使用rising_edge（clk）和falling_edge（clk2）......不同的时钟......这有效吗？
您的代码无法合成的真正原因是因为您在两个进程（上升沿和下降沿）中分配给i2c_scl。
我不明白为什么你觉得有必要使用下降沿逻辑。
虽然在时钟的任何一个边缘计时都是合法的，但通常你只选择一个边缘。
在上升沿为时钟提供时钟并且在下降沿具有第一个翻牌输出的后续翻牌时钟是没有优势的。
这只会将你的最长时间缩短一半。
无论如何，一个更大的问题是你已经在端口列表中声明了i2c_sda作为输出。
它必须是双向的;
从机通过拉下sda来确认字节传输。
奴隶不能在主人总是开车的情况下这样做。
至于阻塞（变量）与非阻塞（信号）分配，一般情况下除非你有一个真正的原因，你使用信号分配。
----------------------------是的，我这样做是为了谋生。



以下为原文

nnunes wrote:Didn't know that. You mean never or for any specific reason in my code? What for instance if I were using rising_edge(clk) and falling_edge(clk2)...different clocks..is this valid?

The real reason your code is not synthesizable is because you assign to i2c_scl in two processes, the rising edge and the falling edge.
 
I don't understand why you feel the need to use the falling-edge logic at all. While it is certainly legal to clock stuff on whichever edge of the clock, in generally you just pick one edge. There is no advantage to clocking something on the rising edge and having the following flop clock the first flop's output on the falling edge. That just cuts your max period in half.
 
Anyways, a much larger problem is that you've got i2c_sda declared in the port list as an output. It must be a bidirectional; a slave acknowledges a byte transfer by pulling down sda. A slave can't do that with the master always driving.
 
As for the blocking (variable) vs non-blocking (signal) assignment, in general unless you have a Real Good Reason you use signal assignments.
----------------------------Yes, I do this for a living.