[问答]

32bit FIFO怎么从SPI闪存启动

问答对人有帮助，内容完整，我也想知道答案 0 嗨，大家好，我想使用FX3与FPGA。我需要提供快速数据传输，所以我决定使用32位从FIFO模式。然而，我有一些疑问： 1。首先，我想从SPI闪存启动。这是第一个问题。32位FIFO不能与SPI一起使用。我假设可以从SPI启动，然后将设备重新配置为32位FIFO。但是，SPI线发生了什么呢？我应该用闪存的WP针来防止无意写入内存吗？ 2。此外，我希望有可能直接从FX3重新配置FPGA。我会使用斯巴达6从串行模式，所以…我需要驱动M1配置线，复位FPGA和从串行线（时钟，串行输出，程序B，iNITHB和完成）。三。这不是我想实现的配置可能性的结束。默认情况下，FPGA将从SPI闪存启动。我希望能够直接从FX3写这个闪存。那么另一个芯片启用和写入保护（？）线是必需的。我的问题是，销我可以使用32位FIFO来满足这种需求？我认为那些销完全可以当FIFO配置GPIO 23；GPIO 25；GPIO GPIO GPIO 45 27 26；。我是理发师吗？可以使用I2S引脚（GPIO 50-52；57）作为GPIO也？它是任何可能使用SPI来满足第三点要求？这仅仅是概念，请把你的建议，我想知道如果它是可能的或不。最好的问候 PNG概念 35.3 K 以上来自于百度翻译以下为原文 Hi all, I would like to use FX3 with FPGA. I need to provide fast data transfer, so I decided to use 32bit slave FIFO mode. However I have some doubts: 1. First of all I'd like to boot from SPI flash. Here is first problem. 32bit FIFO can't be used with SPI. I assumed that it is possible to boot from SPI and then reconfigure device to 32bit FIFO. But what is happening with SPI lines then? Should I use WP# pin of flash to prevent unintended writing to memory? 2. Furthermore, I'd like to have possibility of reconfiguring FPGA directly form FX3. I will use Spartan 6 Slave serial mode, so.. I need to drive M1 configuration line, reset FPGA and Slave Serial lines (CLOCK, SERIAL OUT, PROGRAM_B, INIT_B and DONE). 3. That is not end of configuration possibilities which I would like to implement. FPGA wil boot from SPI flash by default. I'd like to be able to write that flash from FX3 directly. So another chip enable and write protect (?) lines are required. My question is which pins I could use with 32bit FIFO to meet this demands? I think those pins are fully available when FIFO is configured - GPIO 23; GPIO 25; GPIO 26; GPIO 27; GPIO 45. Am I rigth? Is it possible to use I2S pins (GPIO 50-52; 57) as GPIO also? Is it any possibility to use SPI to meet the requirements of the third point? It is only conception, please make your suggestions - I would like to know if it is possible or not. Best regards conception.png 35.3 K 0
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答案对人有帮助，有参考价值 0 嗨，MQ ~，我的问题是，我能用32位FIFO使用哪种引脚来满足这个需求？取决于你的需要。你需要从奴隶FIFO读和写传输吗？我认为当FIFO被配置时，这些引脚完全可用——GPIO 23；GPIO 25；GPIO 26；GPIO 27；GPIO 45。我是理发师吗？对。您可以用IOMATRAIX函数或GPIOORILE来配置它们。是否可以使用I2S引脚（GPIO 50-52；57）作为GPIO？是的，这是可能的。只需使用FX3SDK的GPIOORIDLE函数即可。是否有可能使用SPI来满足第三点的要求？如果您重新配置GPIF在16和32位精细使用硬件SPI，那么您可以使用任何GPIO引脚的芯片选择和写保护线的两个闪存模块。当数据通过SPI传输时，必须设置CS和WP的问题。这意味着用发送/接收SPI函数进行字节计数。如果Flash模块需要对每个传输的断言和CS或WP的重新断言，那么如果您在单次传输模式中全部完成，则需要LunGe时间。因为您必须使用GPIO SET/CLR做CS和WP，需要1微秒来设置或CLR。当做隆皮以上来自于百度翻译以下为原文 Hi mq~, >> My question is which pins I could use with 32bit FIFO to meet this demands? depends on your needs. Do you need read and write transfers in slave fifo? >> I think those pins are fully available when FIFO is configured - GPIO 23; GPIO 25; GPIO 26; GPIO 27; GPIO 45. Am I rigth? yes. You may configure them with the IOMatrix function or the GpioOverride. >> Is it possible to use I2S pins (GPIO 50-52; 57) as GPIO also? yes it is possible. Just use the GpioOverride function of the FX3 SDK. >> Is it any possibility to use SPI to meet the requirements of the third point? If you reconfigure the GPIF between 16 and 32 bit fine to use hardware SPI, then you be able to use any GPIO pin for chip select and write protect lines of the two flash modules. Problems may if CS and WP has to be set while data is transferring through SPI. That means with the function Send-/Receive SPI you have a argument with byte count. If the flash module needs assertion and re-assertion of CS or WP for each transfer, then it takes longe time if you do all in single transfer mode. Because you have to use a GPIO set/clr to do CS and WP wich takes ~1micro second to set or clr. Regards lumpi

2019-2-12 15:24:46 评论举报王建华