无法确定GPIF数据计数器和地址计数器的用途

嗨，C.H.Chen
假设您在FX3主从之间有32位接口。Slave的DMA缓冲区大小分别为1K字节和8个这样的缓冲区。
地址和数据计数器的目的是引入流量控制和防止数据丢失。
地址和数据计数器（它们仅仅是2个计数器和名称不重要）在主机上跟踪有多少字节的数据实际上已经写入奴隶。GPIF状态机中的每个DRMA数据将发送32位数据（4字节），然后地址和数据计数器递增1。当地址计数器达到256（256×4= 1K字节）时，这意味着从存储器中的缓冲器完全被填充。有一个延迟是从切换到下一个缓冲区。主机应该确保它在缓冲区切换期间不驱动数据（通常微秒）。WrdDATAYAWAL只是一个状态，ADDISSH计数器被重置为0，这需要足够的时间来确保从机切换到下一个缓冲器。
类似地，数据计数器加载2048（对于8K缓冲器，2048×4字节）。当数据计数器值命中时，您已经写入了从机中的所有8个缓冲器，返回到RDYWRSIDLE，将计数器重新装入0，并检查标志B（这说明Slave是否释放了任何缓冲器），并相应地驱动数据。
希望这有帮助
当做
穆达比尔卡比尔



     以下为原文
   Hi C.H.Chen
           Lets say you have 32 bit interface between FX3 Master and Slave. And Slave has DMA buffer size of 1K bytes each and 8 such buffers.
    The purpose of address and data counter is to introduce flow control and prevent data loss,.
    The Address and data counter ( They are just 2 counters and names dont matter) in master keeps track of how many bytes of data have actually been written to the Slave. Every DR_DATA in gpif state machine will send out 32 bits of data ( 4 bytes) and then Address and data counters are incremented by 1. When address counter reaches 256 ( 256 x4 = 1K bytes), It means that a buffer in Slave has been filled completely. There is a delay is Slave switching to next buffer. The master should ensure that it doesnt drive data during this buffer switching ( usually few microseconds). WR_DATA_WAIT is just a state where address_counter is reset to 0 and this takes enough time to ensure that  the Slave has switch to next buffer. 
    Similarly data counter is loaded with 2048 ( for 8K buffer, 2048x4 bytes). When data counter value hits, you have written to all 8 buffers in slave, you go back to RD_WR_IDLE , reload the counter to 0 and check flag B ( which tells if Slave has any buffer freed or not) and accordingly drive data. 
    Hope this helps
     
    Regards
    Mudabir Kabir

非常感谢你的解释。这很有帮助。
因此，WrdDATAYAWAIT处理从边侧的缓冲区切换延迟，而InDATA等待状态则处理主方的延迟，对吗？
当EZ-USB FX3发送数据时，发送方在其缓冲区之间切换时也存在这种延迟，对吗？
当做，
陈国忠



     以下为原文
   Thank you very much for the clear explanation. It's very helpful.
    So the WR_DATA_WAIT deals with buffer switching delay on SLAVE side and the IN_DATA_WAIT state deals with the delay on MASTER side, is that right?
    When EZ-USB FX3 is sending out the data, there is also this kind of delay when sender is switching between its buffers, right?
     
    Regards,
    C.H. Chen

嗨，C.H. Chen，
是的，你的理解是正确的。
当做
穆达比尔卡比尔



     以下为原文
   Hi C.H. Chen,
           Yes, your understanding is right.
     
    Regards
    Mudabir Kabir

当主驱动的数据依次存放在从缓冲区的奴隶，主人照顾的缓冲开关在奴隶的延迟和不开任何数据在这段时间。同样，当奴隶是数据驱动的主人，主人应确保奴隶不驱动数据（使用SLRD和野莓控）当主开关的下一个空缓冲区读取数据的进一步前。
当做
穆达比尔卡比尔



     以下为原文
   When the master is driving data to the slave which inturn is stored in slave buffers, Master has to take care of buffer switching delay in the slave and not drive any data during this time. Likewise, when the slave is driving data to the master, master should ensure slave doesn't drive data ( controlled using SLRD and SLOE) when master is switching to its next empty buffer before reading further data.
     
    Regards
    Mudabir Kabir