Vivado生成的XDC约束的严重警告

所有： 
通过尝试各种方法，我能够解决大多数问题。
感谢所有试图提供帮助的人。 
中号-----
在原帖中查看解决方案



以下为原文

All:
 
     By trying various method I was able to solve the majority of the issues.  Thanks to all who tried to help.
 
       M-----
View solution in original post

您是否可能在读取端缺少时钟定义？
Avi Chami MScFPGA网站



以下为原文

Is it possible that you are missing a definition for the clock on the read side?
Avi Chami MSc
FPGA Site

你好@ marvinscheinbart
请查看此ARhttps：//www.xilinx.com/support/answers/66666.html
您需要在驱动FIFO IP读写时钟输入引脚的端口上写入时钟约束。
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以下为原文

Hi @marvinscheinbart
 
Check this AR https://www.xilinx.com/support/answers/66666.html
 
You need to write clock constraints on ports driving FIFO IP read and write clock input pins.
Thanks,
Deepika.
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所有： 
我按照建议修复了时钟的定义，并修复了我所有的严重警告。
如果没有修复由Vivado自动生成的所有约束警告。
例如，我的Aurora核心有以下警告：
[约束18-401] set_false_path：'aurora_core / aurora_module_i / aurora_sim_i / inst / aurora_sim_aurora_lane_4byte_0_i / aurora_sim_hotplug_i / rx_cc_cdc_sync / s_level_out_d1_cdc_to_reg / C'不是有效的端点。
[ “C：/Xilinx/Rover/Rover.srcs/aurora_sim_example/aurora_sim_example.srcs/sources_1/ip/aurora_sim/aurora_sim_clocks.xdc”：57] 
Vivado产生的约束是：
set_false_path -to [get_pins -hier * cdc_to *] 
我打开了Implemented设计并调出了原理图指向我的警告。
我将时钟追溯到它的源（clk125_i），它在我的XDC文件中定义为：
create_clock -period 8.000 -name clk125_i -waveform {0.000 4.0000} [get_pins dbg_pll_i / inst / clk_out3] 
我还执行了'report_clocks'命令，我所有时钟的定义似乎都得到了适当的限制（至少我可以说）。
修复我的Aurora约束的任何建议？



以下为原文

All:
 
     I fixed the definition of the clocks as was suggested and that fixed all of my critical warning.  If did not fix all of my constraint warning that were auto-generated by Vivado.  For example, my Aurora core has the following warning:
 
[Constraints 18-401] set_false_path: 'aurora_core/aurora_module_i/aurora_sim_i/inst/aurora_sim_aurora_lane_4byte_0_i/aurora_sim_hotplug_i/rx_cc_cdc_sync/s_level_out_d1_cdc_to_reg/C' is not a valid endpoint. ["c:/Xilinx/Rover/Rover.srcs/aurora_sim_example/aurora_sim_example.srcs/sources_1/ip/aurora_sim/aurora_sim_clocks.xdc":57]
 
    The constraint generated by Vivado is:
 
set_false_path -to [get_pins -hier *cdc_to*]
 
     I opened the Implemented design and called up the schematic pointed to my this warning.  I traced the clock back to its source (clk125_i) and it's defined in my XDC file as:
 
create_clock -period 8.000 -name clk125_i    -waveform {0.000 4.0000} [get_pins dbg_pll_i/inst/clk_out3]
 
     I also performed a 'report_clocks' command and the definition for all my clocks seem to be properly constrained (as least as far as I can tell).  Any suggestions in fixing my Aurora constraints?

所有： 
通过尝试各种方法，我能够解决大多数问题。
感谢所有试图提供帮助的人。 
中号-----



以下为原文

All:
 
     By trying various method I was able to solve the majority of the issues.  Thanks to all who tried to help.
 
       M-----