ERROR确认：1107 Pack无法将下面列出的符号组合到单个IOB组件中，因为所选的站点类型不兼容

HI，
我使用V-6 SX device.To的FPGA I是两块GTX时钟且本人通过IBUFDS passsing
下面是代码
--------------------------------------------------
------------------------------- IBUFDS_GTXE1组件的实例化---------------
--------------------------------------------------
-------------- INST_GTX_IF_1：ibufdsport地图（O => s_ref_clk1_gtx，I => i_ref_clk1_gtx_p，IB => i_ref_clk1_gtx_n）; ---------------
--------------------------------------------------
---------------- IBUFDS_GTXE1组件的实例化------------------------------
------------------------------------------------- INST_GTX_IF_2
：ibufdsport地图（O => s_ref_clk2_gtx，I => i_ref_clk2_gtx_p，IB => i_ref_clk2_gtx_n）;
ibufds的输出给出了极光核心参考时钟
在地图中我得到了以下错误
反馈错误：1107  - 包无法下面列出到一个单一的IOB组件，因为选择的站点类型是不兼容的符号结合起来。
进一步说明：组件类型由逻辑类型及其包含的逻辑的属性和配置决定。
在这种情况下被选择类型IOB的IO组件，因为IO包含的符号和/或与输入，输出或双向使用一致的性质和含有需要一个更具体的IO组件类型没有其他符号或特性。
请仔细检查逻辑元素的类型及其所有相关属性和配置选项是否与约束的物理站点类型兼容。
总结：符号涉及：PAD符号 “i_ref_clk1_gtx_n”（垫信号= i_ref_clk1_gtx_n）SlaveBuffer符号 “INST_GTX_IF_1 / SLAVEBUF.DIFFIN”（输出信号= INST_GTX_IF_1 / SLAVEBUF.DIFFIN）组件类型涉及：IOB站点位置涉及：AB7站点类型涉及：IPAD
我给出的约束只是周期和锁定时钟
我正在附上地图报告
qdsp_top_module_map.map 6 KB



以下为原文

HI,
  i am using v-6 sx device.To the fpga i am two gtx clocks and that i am passsing through IBUFDS

below is the code
-------------------------------------------------------------------------------
-- Instantiation of IBUFDS_GTXE1 component
-------------------------------------------------------------------------------
INST_GTX_IF_1 : ibufds
port map(
  o   => s_ref_clk1_gtx,
  i   => i_ref_clk1_gtx_p,
  ib  => i_ref_clk1_gtx_n
  );


-------------------------------------------------------------------------------
-- Instantiation of IBUFDS_GTXE1 component
-------------------------------------------------------------------------------
INST_GTX_IF_2 : ibufds
port map(
  o   => s_ref_clk2_gtx,
  i   => i_ref_clk2_gtx_p,
  ib  => i_ref_clk2_gtx_n
  );

the output from ibufds is given aurora core reference clock

in the map i am getting the follwing error

ERROR ack:1107 - Pack was unable to combine the symbols listed below into a
   single IOB component because the site type selected is not compatible.

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOB was chosen because the IO contains symbols and/or properties consistent
   with input, output, or bi-directional usage and contains no other symbols or
   properties that require a more specific IO component type. Please double
   check that the types of logic elements and all of their relevant properties
   and configuration options are compatible with the physical site type of the
   constraint.

   Summary:
   Symbols involved:
       PAD symbol "i_ref_clk1_gtx_n" (Pad Signal = i_ref_clk1_gtx_n)
       SlaveBuffer symbol "INST_GTX_IF_1/SLAVEBUF.DIFFIN" (Output Signal =
   INST_GTX_IF_1/SLAVEBUF.DIFFIN)
   Component type involved: IOB
   Site Location involved: AB7
   Site Type involved: IPAD

The constraint i gave is only period and lock for clocks

i am attaching the map report
            qdsp_top_module_map.map ‏6 KB