无法将符号组合到单个IOB中

嗨，我有这个错误，我正在测试我们设计的主板上的IIC_EPPROM，并利用由我们提供的IP核xps_iic
EDK。
关于我的项目的一些细节：1。哪个软件版本？
ISE 10.1.03 2.哪个设备/包？
xc5vlx50t / ff665
映射期间出现错误消息。
制图设计中融入的LUT ...写文件system_map.ngm运行所...导向填料... ERROR：产品包装：1107  - 无法以下符号组合成一个单一的IOB组件：PAD符号“FPGA_0_IIC_EEPROM_Sda_pin”（垫信号= fpga_0_IIC_EEPROM_Sda_pin）
TBUF符号“iobuf_1 / OBUFT”（控制信号= fpga_0_IIC_EEPROM_Sda_T）BUF符号“iobuf_1 / IBUF”（输出信号= fpga_0_IIC_EEPROM_Sda_I）IOB被选择，因为IO包含的符号和/或与输入，输出，或一致的性质类型的IO组件
双向使用，不包含需要更具体的IO组件类型的其他符号或属性。
每个下面的约束指定了一个非法物理站点类型IOB的组分：符号“fpga_0_IIC_EEPROM_Sda_pin”（LOC = N15 [物理站点类型= IPAD]）组分类型由逻辑类型和属性和配置的确定
它包含的逻辑。
请仔细检查逻辑元素的类型及其所有相关属性和配置选项是否与约束的物理站点类型兼容。
请修正约束accordingly.ERROR：包：1107  - 无法以下符号组合成单个部件IOB：PAD符号 “fpga_0_IIC_EEPROM_Scl_pin”（垫信号= fpga_0_IIC_EEPROM_Scl_pin）TBUF符号 “iobuf_0 / OBUFT”（控制信号= fpga_0_IIC_EEPROM_Scl_T）BUF符号
选择类型IOB的“iobuf_0 / IBUF”（输出信号= fpga_0_IIC_EEPROM_Scl_I）一种IO组件，因为IO包含的符号和/或与输入，输出或双向使用一致的性质，并包含需要更没有其他符号或特性的
特定的IO组件类型。
每个下面的约束指定了一个非法物理站点类型IOB的组分：符号“fpga_0_IIC_EEPROM_Scl_pin”（LOC = P14 [物理站点类型= IPAD]）组分类型由逻辑类型和属性和配置的确定
它包含的逻辑。
请仔细检查逻辑元素的类型及其所有相关属性和配置选项是否与约束的物理站点类型兼容。
请相应地更正约束。
我的.ucf文件是：
Net sys_clk_pin TNM_NET = sys_clk_pin;
净sys_clk_pin LOC = AC18;
Net sys_clk_pin IOSTANDARD = LVCMOS33;
净sys_rst_pin LOC = AC13;
Net sys_rst_pin IOSTANDARD = LVCMOS33;
Net sys_rst_pin PULLUP; ##系统级约束Net sys_clk_pin TNM_NET = sys_clk_pin;
tiMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 8000 ps;
Net sys_rst_pin TIG;
## IO设备约束
####模块RS232_Uart_1约束
净额fpga_0_RS232_Uart_1_sin_pin LOC = W14;
净fpga_0_RS232_Uart_1_sin_pin IOSTANDARD = LVCMOS33;
净额fpga_0_RS232_Uart_1_sout_pin LOC = Y15;
净额fpga_0_RS232_Uart_1_sout_pin IOSTANDARD = LVCMOS33;
####模块IIC_EEPROM约束
净fpga_0_IIC_EEPROM_Scl_pin LOC = P14;
净fpga_0_IIC_EEPROM_Scl_pin SLEW = SLOW;
净fpga_0_IIC_EEPROM_Scl_pin DRIVE = 6;
Net fpga_0_IIC_EEPROM_Scl_pin IOSTANDARD = LVCMOS33;
净fpga_0_IIC_EEPROM_Sda_pin LOC = N15;
净fpga_0_IIC_EEPROM_Sda_pin SLEW = SLOW;
净fpga_0_IIC_EEPROM_Sda_pin DRIVE = 6;
净fpga_0_IIC_EEPROM_Sda_pin IOSTANDARD = LVCMOS33;
你知道这个问题的解决方案吗？
最好的祝福



以下为原文

Hi,
  I have this error, I am testing the IIC_EPPROM on the board we designed, and utilize the IP core xps_iic provided by the
EDK.
  Some details about my project:
  1. Which software version? ISE 10.1.03
  2. Which device/package? xc5vlx50t / ff665

  The error message occurs during the mapping.

Mapping design into LUTs...
Writing file system_map.ngm...
Running directed packing...
ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB
   component:
    PAD symbol "fpga_0_IIC_EEPROM_Sda_pin" (Pad Signal =
   fpga_0_IIC_EEPROM_Sda_pin)
    TBUF symbol "iobuf_1/OBUFT" (Control Signal = fpga_0_IIC_EEPROM_Sda_T)
    BUF symbol "iobuf_1/IBUF" (Output Signal = fpga_0_IIC_EEPROM_Sda_I)
   An IO component of type IOB was chosen because the IO contains symbols and/or
   properties consistent with input, output, or bi-directional usage and
   contains no other symbols or properties that require a more specific IO
   component type.
   Each of the following constraints specifies an illegal physical site for a
   component of type IOB:
    Symbol "fpga_0_IIC_EEPROM_Sda_pin" (LOC=N15 [Physical Site Type = IPAD])
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. Please double check that the types of
   logic elements and all of their relevant properties and configuration options
   are compatible with the physical site type of the constraint.
   Please correct the constraints accordingly.
ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB
   component:
    PAD symbol "fpga_0_IIC_EEPROM_Scl_pin" (Pad Signal =
   fpga_0_IIC_EEPROM_Scl_pin)
    TBUF symbol "iobuf_0/OBUFT" (Control Signal = fpga_0_IIC_EEPROM_Scl_T)
    BUF symbol "iobuf_0/IBUF" (Output Signal = fpga_0_IIC_EEPROM_Scl_I)
   An IO component of type IOB was chosen because the IO contains symbols and/or
   properties consistent with input, output, or bi-directional usage and
   contains no other symbols or properties that require a more specific IO
   component type.
   Each of the following constraints specifies an illegal physical site for a
   component of type IOB:
    Symbol "fpga_0_IIC_EEPROM_Scl_pin" (LOC=P14 [Physical Site Type = IPAD])
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. Please double check that the types of
   logic elements and all of their relevant properties and configuration options
   are compatible with the physical site type of the constraint.
   Please correct the constraints accordingly.

My .ucf file is:

   Net sys_clk_pin TNM_NET = sys_clk_pin;
   Net sys_clk_pin LOC = AC18;
   Net sys_clk_pin IOSTANDARD=LVCMOS33;
   Net sys_rst_pin LOC = AC13;
   Net sys_rst_pin IOSTANDARD=LVCMOS33;
   Net sys_rst_pin PULLUP;
## System level constraints
   Net sys_clk_pin TNM_NET = sys_clk_pin;
   TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 8000 ps;
   Net sys_rst_pin TIG;
## IO Devices constraints
#### Module RS232_Uart_1 constraints
   Net fpga_0_RS232_Uart_1_sin_pin LOC = W14;
   Net fpga_0_RS232_Uart_1_sin_pin IOSTANDARD=LVCMOS33;
   Net fpga_0_RS232_Uart_1_sout_pin LOC = Y15;
   Net fpga_0_RS232_Uart_1_sout_pin IOSTANDARD=LVCMOS33;
#### Module IIC_EEPROM constraints
   Net fpga_0_IIC_EEPROM_Scl_pin LOC= P14;
   Net fpga_0_IIC_EEPROM_Scl_pin SLEW = SLOW;
   Net fpga_0_IIC_EEPROM_Scl_pin DRIVE = 6;
   Net fpga_0_IIC_EEPROM_Scl_pin IOSTANDARD=LVCMOS33;
   Net fpga_0_IIC_EEPROM_Sda_pin LOC= N15;
   Net fpga_0_IIC_EEPROM_Sda_pin SLEW = SLOW;
   Net fpga_0_IIC_EEPROM_Sda_pin DRIVE = 6;
   Net fpga_0_IIC_EEPROM_Sda_pin IOSTANDARD=LVCMOS33;

Do you know a solution for this problem ?  

Best regards