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大家好。
我有与CYUB3014相关的开发经验。为了快速地将FX3集成到我们的系统中,我们使用了CysB3KIT-03。而且工作正常。 大约三周前,CysB3KIT-03被打破了。我买了另一块木板来代替它。但是奇怪的事情发生了。 它不能像预期的那样工作。但是我们使用了相同的FPGA,同样的Verilog程序,与CysB3KIT相同的连接,相同的FixWild镜像文件。 在我们的系统中,使用同步从FIFO模式。然而,FPGA不能从FX3接收数据。根据采样信号线通过ChipScope, 控制信号是正常的,即类低,SLWR高,和野莓,SLRD低,低转带FLAG标签。但没有验证数据总线上的控制中心发送的数据虽然FX3数据。 和以前的断板,系统就正常运行。 为什么会发生这种情况?如何解决这个问题?有什么想法吗?非常感谢。 YZ 以上来自于百度翻译 以下为原文 Hello, everyone. I have related development experience with cyu***3014. In order to quickly integrate FX3 to our system, we used CYUSB3KIT-003. And it worked normally. About three weeks ago, the CYUSB3KIT-003 was broken. and I bought another board to replace it. but something strange happened. It couldn't work as expected. But we just used the same FPGA, same Verilog program, same connection with CYUSB3KIT, same fireware image file. In our system, the synchronous slave fifo mode is used. However, FPGA cannot receive the data from FX3. according to the sampling of the signal line by chipscope, the control signals are normal, that is, slcs is low, slwr is high, and sloe, slrd is low, flagc turns low. but there is no validate data on the data bus although Control Center has sent data to FX3. and for the previous broken board, the system just run normally. why can this happen? how to figure this out? any ideas? Thank you very much. yz |
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11个回答
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加:破碎的CysB3KIT-03版本是CysB3014-BZX I 1437,新的是C 1719。
以上来自于百度翻译 以下为原文 Plus: the broken CYUSB3KIT-003 version is CYUSB3014-BZX I 1437 and the new one is C 1719 |
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你好,郑, 请检查FX3的PKEN引脚是否被拉高。状态机预计这个引脚是高状态切换,数据驱动了FPGA。 最好的问候, 斯里纳斯 以上来自于百度翻译 以下为原文 Hello Zheng, Please check if the PKEND pin of the FX3 is pulled HIGH. The state machine expects this pin to be HIGH to switch the state so that the data is driven out to FPGA. Best regards, Srinath S |
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你好,斯里纳斯 首先,我想对你说声谢谢。我已经根据你的提醒再试一次。它现在起作用了。但仍有一些问题,我想和你谈谈。 在我的系统中,我只使用控制中心上位机发送数据到FPGA FX3,然后读取FX3。所以我选择了流线型模式。根据65974,这pktend讯号来写一个简短的包或10包的Slave FIFO长度。所以它总是保持在高出模式。 基于此,所以我们离开pktend线在前板的FX3和FPGA之间的联系。在Verilog程序,我宣布信号pktend始终保持高。系统运行正常。FPGA可以从FX3读取。 在新的cyu***3kit-003,它对总线没有响应而pktend线叶无关。但当我把pktend线连接,FPGA可以从FX3成功读取。 幸运的是,它现在可以工作了。但为什么会发生这种情况呢?期待着聆听你的想法。 多谢, YZ 以上来自于百度翻译 以下为原文 Hello Srinath S, First, I want to say thanks to you. I have tried again according to your reminder. it works now. But I still have some questions that i want to talk with you. In my system, I just use control center on upper computer to send data to FX3, and then FPGA read from FX3. so I choose the streamOUT mode. According to 65974, This PKTEND signal is asserted to write a short packet or a zero-length packet to Slave FIFO. So it will always keep high in streamOUT mode. Based on this, So we left the PKTEND line unconnected between FX3 and FPGA in the previous board. and in the verilog program, I declare the signal PKTEND always keeps high. The system run normally. FPGA could read from FX3. For the new CYUSB3KIT-003, it has no response on the databus while the PKTEND line leaves unconnected. But when I keep the PKTEND line connected, FPGA can read from FX3 successfully. Fortunately, it can work now. but why it could happen? Looking forward to listening to your ideas. Many thanks, yz |
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uuwerywrsd 发表于 2018-8-18 08:11 你好,郑, 的pkend引脚的FX3 GPIO引脚。默认情况下,对板的GPIO FX3漂浮。所以,这pkend引脚可以被视为高或低,可能会导致错误的结果,因为它发生在你的情况。为了克服这个问题,你应该把pkend引脚为高或修改状态机是独立的pkend销。 最好的问候, 斯里纳斯 以上来自于百度翻译 以下为原文 Hello Zheng, The PKEND pin is a GPIO pin on the FX3.By default, the GPIOs on the FX3 board are floating. So, the PKEND pin may be treated as HIGH or LOW and may cause erroneous results as it happened in your case. To overcome this, you should have to pull the PKEND pin HIGH or modify the state machine to be independent of PKEND pin. Best regards, Srinath S |
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uuwerywrsd 发表于 2018-8-18 08:11 加:其实,我有一个新的cyu***3kit-003板。对于这个板,我有连接在FC3和PFGA之间的PKTACK线。我用ChipScope采样信号。所有的控制信号和旗语信号均正常。和国家机器成功地跳过读取状态。但有没有数据总线。为什么? 根据以上描述,形势变得越来越混乱。有什么想法吗?非常感谢。 以上来自于百度翻译 以下为原文 Plus: actually, I have another new CYUSB3KIT-003 board. and for this board, I have the PKTEND line connected between FC3 and PFGA. and I used chipscope to sample the signals. all the control signal and flag signal were normal. and the state machine successfully skip to the read state. But there are no data on the databus. Why? The situation is getting more and more confused according to above descriptions. ANY IDEAS? Thank you very much. |
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uuwerywrsd 发表于 2018-8-18 08:39 你好,郑, 可你如果地址线[1:0]是正确连接,请检查吗? -如果你仍然面临的问题,请,捕捉UART的记录使用车载USB芯片和共享相同的。 最好的问候, 斯里纳斯 以上来自于百度翻译 以下为原文 Hello Zheng, - Can you please check if the Address lines A[1:0] are connected properly? - In case you still face issues, kindly, capture the UART logs using the on-board USB-Serial chip and share the same. Best regards, Srinath S |
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wangcong12138 发表于 2018-8-18 08:30 另外,实际上,我还有一个新的CYSUB3KIT-03板。和这一局,我已经连接的FC3和FPGA之间的pktend线。我用CHIPSIONT对信号进行采样。所有控制信号和标志信号均正常。状态机成功跳转到读取状态。但是数据没有数据。为什么? 形势变得越来越困惑根据以上描述。有什么想法吗?非常感谢。 以上来自于百度翻译 以下为原文 Plus: actually, I have another new CYUSB3KIT-003 board. and for this board, I have the PKTEND line connected between FC3 and PFGA. and I used chipscope to sample the signals. all the control signal and flag signal were normal. and the state machine successfully skip to the read state. But there are no data on the databus. Why? The situation is getting more and more confused according to above descriptions. ANY IDEAS? Thank you very much. |
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wangcong12138 发表于 2018-8-18 08:54 地址行被分配11。它们连接得很好。非常感谢,先生。 以上来自于百度翻译 以下为原文 The address line are assigned 11. and they connected properly. Thank you so much, sir. |
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你好,郑, 您能使用车载USB串行设备获得UART轨迹吗? 最好的问候, 斯里纳斯 以上来自于百度翻译 以下为原文 Hello Zheng, Can you please obtain the UART traces using the on-board USB-Serial device? Best regards, Srinath S |
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非常感谢。 以上来自于百度翻译 以下为原文 Thank you very much. |
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你好,郑, 你能否用你的发现更新社区,让你知道你的问题是否解决了? 最好的问候, 斯里纳斯 以上来自于百度翻译 以下为原文 Hello Zheng, Can you please update the community with your findings and let know if your problem is resolved? Best regards, Srinath S |
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